In recent years, following downsizing of a memory cell in a DRAM (Dynamic Random Access Memory), a gate length of a memory cell transistor is inevitably reduced. However, if the gate length is smaller, then the short channel effect of the transistor disadvantageously becomes more conspicuous, and sub-threshold current is disadvantageously increased. Furthermore, if substrate concentration is increased to suppress the short channel effect and the increase of the sub-threshold current, junction leakage increases. Due to this, the DRAM is confronted with a serious problem of deterioration in refresh characteristics.
To avoid the problem, attention is paid to a so-called trench-gate transistor (also called as “recess-channel transistor”) configured so that a gate electrode is buried in each trench formed in a semiconductor substrate. According to the trench-gate transistor, it is possible to physically sufficiently secure an effective channel length (gate length) and realize a small-sized DRAM a minimum processing size of which is equal to or smaller than 90 nm.
Moreover, a method of forming a three-dimensional SOI (Silicon On Insulator) structure in each trench and using a silicon layer in the SOI structure as a channel region is proposed in Japanese Patent Application Laid-Open No. H8-274277.
However, the conventional trench-gate transistor has the following problems. Although the short channel effect can be suppressed, it is necessary to further improve the trench-gate transistor for suppression of junction leakage current, reduction in power supply voltage and the like.